The present invention relates to DC to DC converters operating in parallel with one another and sharing load currents.
Current sharing allows a distribution of load current amongst a number of parallel DC to DC converters to increase the current and power delivery to a load by having each of the converters contribute. Current sharing improves the system transient response by spreading the load current over all paralleled converters and improves reliability by reducing their individual power dissipation. With current sharing, each parallel converter contributes approximately a 1/N+1 portion of the load current, when there are a total of N+1 paralleled converters with a minimum of N converters required for providing maximum load current. One converter does not have to contribute a disproportionate amount or reach a current limit before other parallel converters contribute. If one of the paralleled converters should fail, the load current is distributed among the remaining converters and the system continues to operate.
Current sharing can be based on the output current of each of the DC to DC converters or can be based on the current carried by each of the switching devices in each of the converters. When output current or load current is monitored, an output sense resistor is used in each of the paralleled regulators. The load resistor dissipates considerable amounts of power when the converters provide high output currents. Also, with different input voltages supplied to the parallel converters, the main switching transistors of the converters can conduct significantly different currents while each supplying the same output current. Monitoring and controlling the currents in the main switching devices of the converters results in equalizing power device stress which increases system reliability. Balancing the currents in the main switching devices balances the output load currents with each of the converters sharing the load.
In previous systems attempting to accomplish load sharing, buffer amplifiers shown in FIG. 1 by reference numeral 3, 4, and 5 were used to isolate the local and master error bus impedances from the input of a differential amplifier 6. In a master-slave control, the error from one of the converters is used to provide an error signal to all the parallel connected converters. The output of the differential amplifier 6 was used to adjust the value of the voltage reference adjust signal which adjusted the local error signal of each of the converters upwards to meet the value of the master error voltage, so that with all the error signals equivalent, the main power devices of each of the converters will be equivalent. The buffer amplifiers are necessary to isolate the differential amplifier from changing bus impedance which occurs with a differing number of parallel converters and could affect the gain of the differential amplifier. A problem arises with the use of buffer amplifiers due to the voltage offset error inherent in buffer amplifiers. The input offset voltage in the buffer amplifiers of moderate complexity can be as high as 40 mV and varies with temperature and over the life of the device. This results in an uncontrollable offset being added to the error signals by the isolation stage which detracts from the accuracy of the stress sharing system, resulting in inaccurate adjustments to the error signals. The differential amplifier can have a high gain sufficient to provide large inaccuracies due to amplified offset being present at the output of the differential amplifier. This leads to poor system reliability and uneven distribution of load currents and uneven power dissipation by the converter switching devices.
The use of higher complexity buffer amplifiers with extremely low offset voltages adds cost to the integrated circuit and still leaves an undesired offset.
It is an object of the present invention to provide current sharing circuitry which allows precision load current distribution among parallel connected converters.
It is another object of the present invention to provide current sharing circuitry that provides a buffering solution for buffering shared error signals that results in lower cost and higher accuracy than a high complexity buffer amplifier with low offset voltages.